VLSI - Verification

Verification core competency

 Caliber Focus on the last verification languages - e, System verilog, System C and methodologies - OVM and UVM with special emphasis on re-usability of test benches at Block, Sub-system and System level, thereby helping our customers save time in complex ASIC/SoC verification process. Our services includes  

ASIC/SOC Verification

·         Test bench design / development

·         Verification IP development

·         Functional Verification at Block, Sub-system or System level

·         Model-based Verification

·         Hardware-Software Co-Verification/Simulation

·         Coverage-driven Verification

·         Assertion-based Verification

·         Constrained-Random Verification

·         Low Power (CPF / UPF) Verification

·         Test bench migration to e/System Verilog

 

System Validation

      ·         ASIC prototyping on FPGA

      ·         Functional Validation

      ·         Performance Testing

      ·         Conformance & Interoperability Testing

      ·         Load and Stress Testing

      ·         Board Bring up

      ·         Software Integration and Testing

 

VIP Development:

Caliber has established its reputation as a proven VIP development center with advanced.  We offer a complete end to end solution in VIP development services to our Customer. Caliber has been working in various target domain areas over the years based on specific market needs in development of IP’s in Networking, Data Communications, Interconnect, Microcontrollers, Graphics, DSP and Wireless eNodeB

 

Intellectual Property(IP) Core Development

  • VIP Design and Customization
  • VIP Intergration

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